An analog-to-digital converter (ADC) converts an input analog signal to an output digital signal that is an approximation of the input analog signal. The resolution of an ADC defines the accuracy of the approximation between the output digital signal and the input analog signal. In this regard, the closer the resemblance between the output digital signal and the input analog signal, the greater the resolution of the ADC. One of the ADC architectures is a pipeline ADC. Pipeline ADCs generally find application in systems operating at speeds of 10-200 MHz and requiring moderate resolution of the order of 10-14 bits. A major drawback with pipeline ADCs may involve latency occurring at various processing stages. Further, pipeline ADCs may be extremely sensitive to non-linearities affecting offset and gain. pipeline ADC based designs may require complex reference circuitry and precise latch timing in order to ensure output synchronization.
Accordingly, it would be desirable and useful to provide an improved way of providing pipeline ADCs.